Virtual targets remove bottlenecks in early development. With Synopsys Virtualizer, UDE connects to processor models for TriCore, Power Architecture, and Arm. You can debug at source level, configure cores, and analyze timing and performance before boards exist. Profiling and code coverage features remain available thanks to UDE’s trace-aware design.
UDE® Sim provides dynamic binary translation for high simulation speed. It can model the instruction set and, when needed, selected I/O so your software behaves like it would on target hardware. From the UDE user’s view, the simulated system looks like a normal board: set breakpoints, step through code, inspect registers and memory, and run trace-based analyses.
For TriCore-focused teams, TSIM plugs into UDE through the GDI interface. You can tune TSIM settings to match your needs and keep all high-level debugging features. When hardware becomes available, replace the virtual interface with a hardware access device and continue with the same projects, layouts, and workflows.
